FIG. 1 illustrates an example of conventional level shifter circuit. PMOS transistor 1 and 2 and an NMOS transistor 3 are connected in series between a supply terminal 4 providing a first potential V.sub.LC, and a ground potential point, to thereby form a first circuit 51 which acts as a CMOS inverter circuit when the PMOS transistor 2 is ON, as will be described later. (Hereinafter, the first circuit 51 is referred to as first inverter circuit 51.) Similarly, PMOS transistor 5 and 6 and an NMOS transistor 7 are connected in series between the supply terminal 4 and the ground potential point to form a second circuit 52 which acts as a CMOS inverter circuit when the PMOS transistor 6 is ON, as will be described later. (Similarly, the second circuit 52 is referred to as second inverter circuit 52.) A junction between the drain of the PMOS transistor 2 and a drain of the NMOS transistor 3 forms an output node 8 of the first inverter circuit 51. The output node 8 is connected to a gate of the PMOS transistor 6 of the second inverter circuit 52. Similarly, a junction between a drain of the PMOS transistor 6 and a drain of the NMOS transistor 7 forms an output node 9 of the second inverter circuit 52, which is connected to a gate of the PMOS transistor 2 of the first inverter circuit 51. In this example, an output 10 at which a level-shifted output signal S.sub.out is developed is connected to the output node 9 of the second inverter circuit 52.
An input terminal 11, at which an input signal, such as S.sub.IN shown in FIG. 2(a), is applied, is coupled to a gates of the PMOS transistor 1 and the NMOS transistor 3 of the first inverter circuit 51 and also to an input of a CMOS inverter 12. An output of the CMOS inverter 12 is coupled to gates of the PMOS transistor 5 and the NMOS transistor 7 of the second inverter circuit 52. The CMOS inverter 12 is operated from a second voltage V.sub.DD which is supplied from a voltage supply terminal 13. The input signal S.sub.IN has an H-level at V.sub.DD and an L-level at the ground potential. An output signal S.sub.IN of the CMOS inverter 12 is the inversion of the input signal S.sub.IN, and has an H-level at V.sub.DD and an L-level at the ground potential.
Let it be assumed that the level shifter circuit of FIG. 1 is used, for example, as a liquid crystal driver circuit and that the first potential V.sub.LC is 3 volts. Also, let it be assumed that a voltage V.sub.DD, which is the operating voltage for the circuit (not shown) for producing the signal S.sub.IN and for the inverter 12 for producing the inverted signal S.sub.IN, is 2 volts. Then, the level shifter circuit of FIG. 1 operates to produce, from the input signal having an H-level of 2 V, an output signal S.sub.OUT having an H-level fixed at 3 V. In other words, the level shifter circuit of FIG. 1 operates to shift the H-level from 2 V to 3 V.
In operation, when the input signal S.sub.IN goes down to the ground level, the ground potential is applied to the gates of the PMOS transistor 1 and the NMOS transistor 3 of the first inverter circuit 51, whereas V.sub.DD =2 V is applied to the gates of the PMOS transistor 5 and the NMOS transistor 7 of the second inverter circuit 52. This turns on the PMOS transistor 1 and turns off the NMOS transistor 3. Although V.sub.DD =2 V is applied to the gate of the PMOS transistor 5, the PMOS transistor 5 exhibits high resistance and is not turned off completely, since V.sub.LC =3 V is applied to its source. On the other hand, the NMOS transistor 7 becomes fully conductive. The NMOS transistor 7 is designed to have a sufficiently small ON-resistance such that even when the PMOS transistor 6 is conductive, the output signal S.sub.OUT is substantially at the ground potential. When the output signal S.sub.OUT is at the ground potential, the PMOS transistor 2 is turned on. Because the PMOS transistor 1 is conductive and the NMOS transistor 3 is non-conductive as stated previously, the output node 8 of the first inverter circuit 51 assumes V.sub.LC upon the turning on of the PMOS transistor 2. This causes the PMOS transistor 6 to be turned off. As the PMOS transistor 6 is turned off, the output signal S.sub.OUT at the output terminal 10 is maintained at the ground potential even when the PMOS transistor 5 has not yet turned off completely.
When the input signal S.sub.IN goes to V.sub.DD, V.sub.DD is applied to the gates of the PMOS transistor 1 and the NMOS transistor 3 of the first inverter circuit 51, while the ground potential is applied to the gates of the PMOS transistor 5 and the NMOS transistor 7 of the second inverter circuit 52. This causes the PMOS transistor 5 to be turned on and the NMOS transistor 7 to be turned off. However, since the previous state of the PMOS transistor 6 is the OFF state, the output node 9, i.e. the output terminal 10 is instantaneously floating. On the other hand, V.sub.DD =2 V is applied to the gate of the PMOS transistor 1 of the first inverter circuit 51, but its source potential is V.sub.LC =3 V. Therefore, the PMOS transistor 1 exhibits high resistance but it does not become fully non-conductive. Because of V.sub.DD applied to the gate of the NMOS transistor 3, it becomes fully conductive. The NMOS transistor 3 is designed to have such a small ON-resistance, that under this condition, even if the PMOS transistor 2 is conductive, the output node 8 of the inverter circuit 51 is substantially at the ground potential. With the output node 8 being at the ground potential, the PMOS transistor 6 is turned on. At this time, the PMOS transistor 5 is conductive, and the NMOS transistor 7 is non-conductive. Accordingly, the potential at the output node 9 and, at the output terminal 10 is V.sub.LC =3 V. Thus, the output signal S.sub.OUT results, which has the H-level at V.sub.LC =3 V which is a level-shifted version of the H-level of the input signal S.sub.IN at V.sub.DD =2 V. As the output terminal 10 goes to V.sub.LC, the PMOS transistor 2 is turned off. Under this condition, even when the PMOS transistor 1 is not fully non-conductive, no current will flow from the first supply terminal 4 through the first inverter circuit 51 to the ground potential point. The output signal S.sub.OUT on the pulse varying between the ground potential and V.sub.LC =3 V may be used as a signal for driving a liquid crystal device.
In the conventional level shifter circuit of the above-described configuration, current will flow from the first supply terminal 4 to the ground potential point through the PMOS transistors 5 and 6 and the NMOS transistor 7 of the second inverter circuit 52 at an instant when the input signal S.sub.IN changes from V.sub.DD (=2 V) to the ground potential, and, also, current will flow from the first supply terminal 4 to the ground potential point through the PMOS transistors 1 and 2 and the NMOS transistor 3 of the first inverter circuit 51 at an instant when the input signal S.sub.IN changes from the ground potential to V.sub.DD. This disadvantageously increases operating power consumption of the level shifter circuit.
The present invention is to eliminate the above-described disadvantage and to provide a level shifter circuit with reduced operating power consumption.